Threshold gates and circuits



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' THRESHOLD GATES AND CIRCUITS Filed July 13, 1966 5 Sheets-Sheet 5 INVENTOR.

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At'idrntl/ United States Patent p" 3,487,316 THRESHOLD GATE AND CIRCUITS Robert 0. Winder, Trenton, N.J., assignor to RCA Corporation, a corporation of Delaware Continuation-impart of application Ser. No. 343,030, Feb. 6, 1964. This'application July 13, 1966, Ser.

' Int. Cl. H031: 19/20 U.S. Cl. 328-92 18 Claims ABSTRACT OF THE DISCLOSURE This application is a continuation-in-part of application Ser. No. 343,030, fild Feb. 6, 1964, and now abandoned.

This invention relates to threshold gates which perform both storage and logic functions and to circuits which incorporate such gates.

A threshold gate is a circuit with a plurality of input signal leads and one or more output signal leads. Signals representing binary digits are applied to the respective input leads, each such signal having an effective weight of l or some multiple of l. The output signal or signals indicate whether the effective number of ones represented by the input signals, that is, whether the sum obtained when adding the weights of all input signals representing a 1, is equal to or greater than a predetermined value known as the threshold level. A

A majority gate is a particular type of threshold gate which has an odd number n, of inputs, each of which has a weight of 1, and whose threshold is ('n+1)/2L The 3,487,316 Patented Dec. 30, 1969 different values of control signals, perform different functions.

Another object of this invention is to provide a threshold gate circuit which performs the function of a flip flop and of the input gates to the flip-flop.

Another object of this invention is to provide a threshold gate circuit which operates as a set-reset flip-flop.

Another object of the invention is to provide threshold gate circuits which perform multiple functions such as storage, MAJORITY, AND, OR and so on.

Another object of this invention is to provide a new and improved shift register made up of threshold gate circuits such as described above.

Another object of this invention is to provide an asynchronous cascaded network made up of threshold gate circuits such as described above.

Another object of the invention is to provide a high speed multiplier made up of threshold gate circuits such I as described above.

The circuits of the invention each include a threshold gate and means for applying n input signals x x x with the respective weights W W w to the gate, where n is 0, 1 or more than 1 and W1, W2 w are integers. The output signal of the threshold gate is fed back to the input to the gate with weight w, where w is an integer greater than the sum of w +w +w In addition, m control signals c c are applied to the gate with respective weights v v where m is an integer greater than 1, and v v are integers.

The invention is discussed in greater detail below and is shown in the following drawings of which:

FIGURE 1 is a block diagram of a majority gate connected to operate as a gateable bistable circuit;

output signal, in other words, has a binary value which is (W1'+W2 may be called a fneutral threshold gate.) I A minority gate has the same characteristics as a majority gate except that the output produced by the minority gate is complementary to that produced by the majority gate. For example, in the case of a 5-input minority gate,

each input of weight 1, if 3 or 4 or 5 of the inputs represent a l, the output represents a 0; if 3 or 4 or 5 of the inputs represent a 0, the output represents a' 1.

The general object of this invention isto provide multiple function building blocks for electrical systems such as data processing systems.

A more specific object of this invention is to provide threshold gate circuits which have control signal inputs, zero,'one or more than one information signal inputs, and a feedback signal input and which, in response to FIGURE 2 is a truth table representing the operation of the majority gate of FIGURE 1;

FIGURE 3 is a schematic circuit diagram of one embodiment of the majority gate of FIGURE 1;

FIGURE 4 is a block diagram of a shift register utilizing the majority gate circuits of FIGURE 1;

FIGURE 5 is a block diagram of a majority gate circuit which functions as a gateable flip-flop;

FIGURE 6 is a schematic circuit diagram of a threshold gate which may be utilized in practicing the invention;

FIGURE 7 is a truth table illustrating the operation of the threshold gate of FIGURE 6;

FIGURE 8 is a schematic circuit diagram of a bistable circuit embodying the threshold gate of FIGURE 6;

FIGURES 9-13 are block diagrams of other threshold gate circuits according to the invention;

FIGURE 14 is a block diagram of a cascaded asynchronous logic network according to the invention;

FIGURE 15 is a drawing of the conventions employed 11 FIGURE 16; and

FIGURE 16 is a block diagram of a multiplier according to the invention.

The blocks making up the figures are circuits which re- :eive electrical signals indicative of binary digits (bits) and which produce outputs indicative of bits. For the sake of brevity, it is sometimes stated in the explanation which follows, that a 1 or 0 is supplied to or obtained from a stage rather than saying that a signal representing a 1 or 0 is applied to or obtained from the stage.

The present invention is perfectly general in thesense. that it is applicable to both majority (and minority) gates and to other types of threshold gates. In FIGURES 1 and 5 the threshold gates employed are, in fact, majority gates and are so legended. In both of these figures the output signal is shown feeding back to two input terminals. It is to be understood, of course, that this is merely a way of indicating that the weight of' the feedback signal is 2. In practice, there can be two terminals present. However, as an alternative there may be only one terminal physically present and the weight 2 assigned to that terminal, for example by placing a resistor in series therewith which is half the effective value of the resistors in series. with the other terminals.

FIGURES 9-12 indicate the weights of the input signals by numbers applied next to the corresponding input terminals. For example, in FIGURE '11, the signal y fed back has the weight 4 and this is indicated by the number 4- next to the y input terminal. In these figures the threshold of the gate is indicated by the letter T=some number, where the number represents the threshold value. For example, in FIGURE 11 the gate illustrated may be termed a neutral threshold gate and has a threshold of 6. As another example, in FIGURE 13 the gate illus trated is not a neutral threshold gate and has a threshold of 4.

The gates of the invention are shown to have a single output. However, it is to be appreciated that each gate may, in addition, have a complementary output and that the logical inversion necessary to obtain the complementary output may be performed within the gate as discussed, for example in copending application 490,052, and now Patent No. 3,403,267 Binary Counter and Flip Flop filed Sept. 24, 1965, by the present inventor.

The simplest circuit of the present invention is shown in FIGURE 9. It comprises a 3-input majority gate 110 having inputs c c and y, all of weight 1. The signal y is a feedback signal which comes from the output signal terminal Y. (Here and elsewhere in the discussion, a terminal and the signal applied to or obtained from the terminal are identified by the same letter.)

In the operation of the gate of FIGURE 9, if C17 C2, that is, if c and c =l, or vice versa, the information stored in the circuit cannot be disturbed. For example, if 3 :1 and if one of c, and c =l, then two of the three inputs to gate 110 represent 1 and the output must remain a 1. In a similar manner, if 32:0 and one of the two inputs 0, and c is a 0, then two of the three inputs to gate 110 are 0 the output Y must remain 0.

To store new information in the gate 110, both 0 and c must be made to have the same value. If c =c =1 then Y must become 1 since at least two of the three inputs are 1. If c =c =0 then Y must become 0 since at least two of the three inputs to gate 110 are equal to 0. After new information is entered into the gate 110, it may be retained in the gate by making c =l and c =0 or vice versa in the manner already indicated.

The operation of the gate of FIGURE 9 can be described in Boolean terms in the following way. When c is the same value as 0 then When 0 is to c then where Y is the present value of Y and y is the former value of y. I

A second embodiment of the invention, shown in FIG- URE 1, consists of a majority gate having inputs with a total weight of 5, and performs the function both of a flip-flop and of the input gates to the flip-flop. The input terminal x receives an information signal; the input terminals a and b receive control signals; the input terminals y, and y which can be considered as a single terminal which applies a signal of weight 2 to the gate, are feedback terminals which receive the signal from the output terminal Y of the gate 10. The feedback signal permits the majority gate to operate as a flip-flop, that is, as a bistable storage element; the values of the control signals determine whether information signals can or cannot be gated into the flip-flop.

In the operation of the gate of FIGURE '1, when a b, that is, when a=0 and b=l, or vice versa, the information signal x cannot affect the state of the gate. This is so because the control inputs then cancel and the majority gate 10 acts like a 3-input majority gate, the value of two of whose inputs is fixed. Thus, if y=1, two of the three inputs are 1, or in terms of the S-input gate shown, three of the five inputs are fixed at 1, and xhas no effect, I g

If a:b=1,' thenif y was previously a 1, it'will remain a 1- regardless of the valu'eof x or if x is a 1, y will become 1 regardless of its former value. In terms of .operation as a flip-flop, the flip-flop will be set when a and b both equal 1 and the information signal x is also equal to 1. The signals a=b=l can be considered priming sig nals for a 3-input AND gate to a flip-flop, and the signal x=l as the enabling signal forthis gate which causes the gate to apply a set signal to the set terminal of the fl p-fl When a and b are 0, then if. y previously was a 0, it will remain 0.,If a and b are 0 and x. is also a 0, y will become a 0 regardless of its former'value. Thus, this situation can be compared to resetting a flip-flop. The signals a=b=0 can be considered as priming signals for a 3-input NOR gate to a flip-flop and the signal x =0 .as the enabling signal to the NOR gate which causes the NOR gate to apply a reset signal to the reset terminal of the flip-flop. p

In Boolean terms, the operation of the gate of FIG- URE 1, under the'various conditions discussed above, may be described as follows: I

When a b y=y* v where y is the present value of y and y* is the former value of y.

When a-=b=l, then When a=b=0', then I y=x'y* The truth table of FIGURE 2 also illustrates the operation of the circuit. The bracketed portion of the table legended A corresponds to Equation 4; the bracketed portion of the table legended B corresponds to Equation 5; the bracketed portion of the table legended C corresponds to Equation 6.

If during the application of an information signal x, first cy=c =0 and then c ==c =1, or vice versa, then the circuit will store x. In Boolean terms, Equations 5 and 6 are combined to give Thereafter c may be -made unequal to 0 so that the information present in the circuit will continue to be stored. V I

A third embodiment of the invention is shown in FIGURE 5. This embodiment can operate as a memory element such as a flip-flop, an OR circuit, an AND circuit, a flip-flop which can be unconditionally set and a flip-flop which can be unconditionally reset. The circuit has a single output terminal y and inputs of total weight 7. The feedback signal, which is shown connected to two input terminals "y, and y has. a weight of 2. The information signal x has a weight of 1 and the control signals a, b, c and at each have a weight of 1.

For operation of the circuit above as a memory element, two of the four control signal inputs are made to represent a 0 and the remaining 2 control signals to represent a 1. In this condition, at least four of the 7 input weights are of the same value as 'y so that x cannot disturb the circuit operation. The circuit of FIG URE 5 can be unconditionally reset by making all four control inputs 4, b, c and d equal to O. This forces y to be a 0 since at leastfour of the seven input weights are 0. To set the circuit ofFIGURE 5, the four control inputs a, b, c and d are all made to assume the value 1 so that y becomes 1. v

If three: of the four input control signals are 1, then if x is a l, y becomes 1, or if y is already 1, y remains 1. If three of the four control signals are 0, then if x is a 1 and y is a 1, y remains 1 and under all conditions, y becomes 0.

The operation of the circuit of FIGURE 5 may be described in Boolean terms by the following equations. When two of the four inputs are 1 and the other two are 0 then: 7

When all four control signals are 0, then:

y= When all four control signals are 1, then:

-1 When'three of the four control signals are 1, then:

, v y +y* (1 When three of the four control signals are 0, then:

' i r I r= 'y* As in the case of the circuit of FIGURE 1, if, the circuit is operated as indicated by Equation 10 and then as indicated by Equation 11 then:

y=( +y*)-x=x (11a) which means that the circuit will store the x signal.

The circuit of FIGURE 5 has six inputs with respective weights 1, 1, 1, 1, 1, 2. Instead, a five input majority gate may be employed with weights 2, 1, 1, l, 2, where a single control signal of weight 2 is substituted for signals a and b, for example, and the remaining signals c, d, x and y have weights 1, l, 1 and 2, respectively. A modified circuit of this type is employed in the circuit of FIGURE 14. As will become clear in the discussion of FIGURE 14, the operation of the modified circuit is exactly the same as that of the FIGURE 5 circuit since in both cases, of the weight 4 assigned to control signals, binary 1 (or 0) signals may have a total weight of0,1,2,3or4. I

A fourth embodiment of the invention is shown in FIGURE 10. It is a S-input threshold gate having inputs c 0 x x and y with respective weights 1, 1, 1, 1, 3. The inputs c and 0 are control signal inputs; the inputs x and x are information signal inputs; the input y is a feedback signal.

In the operation of the circuit of FIGURE 10, when c c the circuit stores the information then present. In other words If c =c '0, then Y=I if y=1 and one of x or x is 1.

In Boolean terms Y= txl+xa (13) If c =c =1, then Y is lit x and x are 1 or if y is 1.

In 'Boolean terms I If the control signals are made c =c =0 and then changed to c -=c -=l or vice versa.,then the circuit operates as a majority circuit. In the case in which 0 :0 0, Y is 1 if x and y are 1 or if x and y are 1. In the case in which c =c 1, y is 1 if x and x are 1. This majority function, in Boolean terms, is

Another embodiment of the invention is shown in FIG- URE 11. It is a 7-input threshold gate having inputs 6 c c 0 x x x and y with respective weights 2, 1, 1, 1, 1, 1, 4. The first three inputs c c c are control signal inputs; inputs x x x are information signal inputs; input y is a feedback signal.

The operation of the circuit of FIGUREv 11 is succinctly given in the following Boolean equations. When 0 :1 and c =c =O or vice versa, the control inputs cancel and When the three control inputs all equal 0, then Y=y-MA](x x x (17) When c =c =c =1 then If three of the four control weights represent 1, that is, for example, if 0 and are 1 and 0 is 0 then If three of the four input control weights represent 0, as for example, when 0 :0, 0 :0, 03:1, then The circuit of FIGURE 11 can also be operated by first making all of the control signals a 1 and then all a 0, or vice versa. These two steps combined cause the circuit of FIGURE 11 to operate as a majority gate, as defined by the following equation which readily may be derived from Equations 17 and 18 The circuit of FIGURE 12 comprises a 7-input threshold gate having inputs c c c 0 x x and y with respective weights 2, 2, 1, 1, 2, 1, 4. The signals c c c and 0 are control signals; the signals x and x are information signals; the signal y is a feedback signal. As in the previous cases, when the sum of the weights of the control signals representing 1 is equal to the sum of the weights of the control signals representing 0, the circuit operates as a memory element. For example, when c =c =0 and c =c =1, then When five of the six input weights of the control signals represent a 0 and the remaining control signal represents a 1 then When five of the six input weights of control signals There are a number of otherways in which the gate of FIGURE 12 may be operated depending upon the permutations of control signals. In view of the many examples already given, these should be evident to the reader.

The circuit of FIGURE 13 is a six input threshold gate having inputs c c x x x and y with respective weights 1, 1, 1, 1, 1, 4. This is not a neutral gate as the total of input weights is 9 and the threshold is 4. In other words, if four or more of the total 'of 9 input weights represent a 1, the output Y is a 1.

In the operation of the circuit of FIGURE 13 if c =c =0 then i t There are many diiferent ways in which the thresholdgate circuits of the invention may be implemented. The

actual circuits may employ transistors or vacuum tubes or magnetic cores or cryotrons or two terminal devices such as conventional diodes or tunnel diodes and so on. For purposes of illustration, a number of circuits employing transistors are shown. The first such circuit is illustrated in FIGURE 3. The terminals of this particular circuit have been chosen to correspond to the terminals of the embodiment of FIGURE 1, however, with minor modification the circuit of FIGURE 3 is applicable to all other embodiments of the invention. These modifications entail adding additional input terminals and other similar engineering changes.

The circuit of FIGURE 3 includes a plurality of input terminals a, b, x, y and y corresponding to the identically legended terminals in FIGURE '1. Each of the input terminals is coupled througha separate resistor, respectively legended 14, 16, 18, 20 and 22, to the base electrode 23 of a first transistor 24.

The first transistor 24 may, for example, be of the PNP type conductivity and includes an emitter electrode 26 coupled to the midpoint 28 of a voltage divider 30. The voltage divider 30 includes a pair of equal valued resistors 32 and 34 connected in series between a source of negative potential V and a point of reference potential, chosen as ground. The first transistor 24 also includes a collector electrode 36 coupled through a load resistor 38 to the potential source V The collector electrode 36 of the first transistor 24 is also directly coupled to the base electrode 40 of a second transistor 42.

The second transistor 42 is of the NPN type conductivity and includes an emitter electrode 44 coupled directly to the negative potential source V and a collector electrode 46 connected through a load resistor 48 to ground. The output terminal y is connected to the collector 46 of the second transistor 42 and when operated as shown in FIGURE 1 is also connected back to the input terminals y and y The values and types of components utilized in the bistable circuit 10 are show in FIGURE 3.

In describing the operation of the circuit 10 of FIG- URE 3, it is assumed that ground represents the binary digit and a voltage of approximately V the binary digit 1. The output signal y is at ground when transistors 42 and 24 are both cut-off and in this condition the circuit is storing a O. The output terminal y is at a voltage of approximately V v.) when the transistor 42 conducts heavily at saturation and in this condition the circuit 10 is storing a 1. In the same manner, the application of a signal level V or 20 volts to an input terminal represents the application of a binary 1, Whereas the application of a signal at the zero or ground level represents the application of a binary O.

The connection of the emitter electrode 26 of the first transistor 24 to the midpoint of the voltage divider establishes a threshold level, namely one-half the potential of the supply V which must be overcome before the transistor 24 can be made to conduct. With the magnitude of the potential source V at 20 volts, the emitter electrode 26 of the first transistor 24 is at threshold potential of 10 volts. Thus, to forward bias the base-emitter junction of the transistor 24 requires that the base electrode 23 become more negative than 10 volts.

For operation in the manner depicted in Equation 5 (y=x+y*) a binary 1 is applied to terminals a and [7. Thus, each of the terminals a and b is at the V or 20 volt potential level. Assume that the transistors 42 and 24 are initially nonconducting so that the circuit 10 is storing a binary 0 and terminals y and y are at ground. Under these conditions, the base electrode 23 is at a 10 volt level. When a binary 1 (-20 volts) is applied to the information signal input terminal x from, for example, another circuit such as circuit 10, the potential at the base electrode 23 becomes more negative and assumes a value of approximately l2 volts. The threshold level therefore is exceeded and transistor 24 conducts. The conduction of the transistor 24 forward biases the baseemitter junction of the second transistor 42 and the second transistor 42 conducts. Its collector electrode 46. and-hencethe output terminal Y is thereupon driven from ground to substantially the 20 volt level and the circuit 10 stores a binary 1.

If the circuit of FIGURE 3 is initially storing a O, and a=b=l, and x is a 0 (ground) then the circuit state is unaffected. Both transistors remain nonconducting.

For the operation described in'Equation 6. (y=x-y*), a binary 0 (a signal at ground potential) is applied ta terminals a and b. Assume circuit 10 is storing a binary 1 and hence the feedback signals y and y also represent binary 1. Under these conditions, when a binary 0 signal is applied to the information input signal terminal x, the bistable circuit 10 switches from the conducting state, wherein a binary 1 signal is stored, to a nonconducting state, wherein a binary 0 signal is stored. With a binary 0 signal applied to the terminal x, the potential at the base electrode 23 of the transistor 24 becomes 8 volt. This potential reverse biases the base-emitter junction of the first transistor 24 and cuts off-this transistor. The base electrode 40 ofthe second transistor 42 follows the collector 36 potential of the first transistor 24 and becomes negative and this drives transistor 42 to cut-off. When this occurs, y becomes equal to binary O (is at ground) and circuit 10 stores a binary 0. The'stored binary 0 signal is also applied to the input terminals y and y and the circuit is locked in the 0 state.

In the type of operation depicted by Equation 4 (y=y*), signals of opposite binary values are applied to the terminals a and b. The control signals a and b therefore effectively cancel each other and relinquish control of the bistable circuit 10, and the feedback signals y and y determine the circuit state. These signals hold the circuit 10 in its initial operating state regardless o the value of input signals x.

The operation of the circuit 10 with the various other possible combinations of input and feedback signals is self-evident from the description above.

The first transistor 24 in FIGURE 3 functions as a switching element to turn on and off the second transistor 42. As a switching element, the transistor 24 draws little current and consequently the threshold reference point 28 of the voltage divider 30 remains substantially at the 10 volt threshold level. The second transistor 42 draws appreciable current from the supply V so as to provide a high current output to drive other circuits.

FIGURE 6 is a schematic circuit diagram of another transistorized threshold circuit which, when operated in the manner shown in FIGURE 8, may be utilized in practicing the invention. While only three inputs x x and 0 are shown, the principles of operation hold for many more inputs than this.

The threshold gate 80 conduts when the sum of the input signals exceeds a threshold level. The threshold gate 80 includes a pair of input signal terminals x and x which are coupled through the input resistors 82 and 84, respectively, to the base electrode 86 of a first transistor 88. The resistors 82 and 84 may, for example, be of equal value. The emitter electrode 90 of the first transistor 88 is coupled to a control signal or threshold signal generator 91. The collector electrode 92 is coupled through a load resistor 94 to ground, as well as through a coupling resistor 96 to the base electrode 98 of a second transistor 100. The emitter electrode 102 of the second transistor is grounded, while the collector electrode 104 thereof is coupled through a load resistor 106 to a source of positive potential V Anoutput terminal yg is provided at the collector 104 of the second transistor 100.

The threshold gate 80 functions as either an AND gate or an OR gate for the x and x input signals, depending on the level of the control or threshold signal applied to the emitter 90 by the generator 91. Assuming that ground potential is a binary 1 signal and +2 volts is a binary signal, the application of a threshold signal level of, for example, +1.9 volts to the emitter 90 of the first transistor 88 causes the threshold gate 80 to function as an OR gate. This may be seen from the truth table shown in FIGURE 7a. When two binary 0 signals are applied to the terminals x x the base 86-emitter 90 junction is reverse biased and no conduction occurs. Thus, the signal level at the output terminal 2 is +2 volts or a binary 0. When a binary 1 (ground level signal) is applied to either x or x; or both and the emitter 90 is at +1.9 volts, the baseemitter junction of the transistor 92 becomes forward biased. The conduction of the transistor 88 then drives the second transistor 100 into saturation. The signal level at the output terminal is therefore at ground level producing a binary 1.

When the threshold signal from the generator 92 is reduced to a lower voltage level, such as, for example, +0.49 volts; the gate 80 functions as an AND gate. FIG URE 7b' shows the truth table for AND operation. When two binary 0 signals (i.e., +2 volt signals) and applied FIGURE 8 is a schematic circuit diagram of a threshold gate 80', corresponding to thegate80'of FIGURE 6, which is connected tooperate as a circuit such as shown in FIGURE 1. Circuit elements which are similar in the twocircuits are identified by the same reference numerals,

'unprimed in FIGURE 6 and primed in FIGURE 8. In

the present circuit, however, the input" terrriinalx'is coupled to the output terminal 3 to provide a feedback signal similar to the "feedback signalinthe circuit 10. Additionally, theresistors 110 and 112 coupling the terminals x and x respectively, to the base electrode 86 of the first transistor 88' are not equal. The resistor 112,is"appreciably smaller thanthe resistor 110 making the feedback signal" applied tothe terminal x of greater" weight than an input information signal applied to the input te'rrninal x;. The resistor "112 rather than being one-half the value of the resistor 110 is instead about one-third'o f the value of resistor 110 to insure proper circuit operation, even with reasonable variation of circuit parameters.

A control signal generator 114, in FIGURE 8, applies a control signal P to the emitter 90' of'the" first transistor 88. The signal P shown in FIGURE-8, while of analog .form, simulates the effect of the binary signals applied to control terminals a and b in the circuit 10 of FIG- URE 3. The control signal P exhibits three different signal levels, a quiescent level, a high level, and.a low level. For the values of components shown in'FIGURE 8, the

quiescent, high and low voltage levels of the, control sigof the gate 80 of FIGURE 6. In this operation, an input binary 1 signal applied to x is transferred into the circuit 80', whereas an input binary 0 signal does not affect the state of the circuit. The high level of P corresponds,

in binary terms, to the application of a=b=1 to the circuit of FIGURE 1.

The low level of the control signal P operates the threshold gate circuit 80' in a manner similar to the AND gate operation of the gate 80 of FIGURE 6. In this operation, an input binary '0 signal applied to the input terminal x is transferred into the gate 80', whereas an input binary 1 signal does not affect the state of the circuit. This operation corresponds, in binary terms, to the application of a=b=0 to the circuit of FIGURE 1.

If the control signal P rises from the quiescent level so as to become more positive than V the threshold gate bistable circuit 80' is rendered conductive or unconditionally set. This corresponds to a=b=c=d=l in FIGURE 5. Alternatively, if the control signal P drops from the quiescent level to become zero or negative, the threshold gate bistable circuit 80 is rendered nonconductive or unconditionally reset. This corresponds to a=b=c=d=0 in FIGURE 5. Such a setting or resetting of the circuit 80' may also be utilized to transfer binary signals into the circuit 80'. For example, if the circuit 80 is first set, then the application of a low level control signal (i.e., an AND level signal or .49 volt) transfers a binary 0 signal into the circuit if the input signal x is a binary 0 signal. If the input signal x is a binary 1 signal, no change occurs. Alternatively, if the circuit 80' is first reset, then the application of a high level control signal (i.e., an OR level signal or 1.9 volts) transfers a binary 1 signal into the circuit if the input signal x is a binary 1 signal. If the input signal x is a binary 0 signal, no change occurs.

There are many uses forthe threshold gate circuits of the invention. A number of such uses, not meant to be exhaustive, are illustrated in the remaining figures.

FIGURE 4 shows a circuit which employs the threshold gate circuits 10 of FIGURE 1. The circuit comprises two registers and 60, each with four stages, legended 50a through 50d and (Wm-d, respectively. Together, they operate as two stages of a shift register which shifts four bits in parallel, from left to right in FIGURE 4.

The output terminal y of each stage in register 50 is connected to the input terminal x of the corresponding stage in register 60. The output terminal y of each stage is also coupled back to the feedback terminals y and y of the same stage.

The control signal'terminal a of each of the stages in the shift register 60 is connected to a shift line the control signal terminal b in each of the stages in the shift register 60 is connected to the shift line 72. The shift line 70 is connected through a delay circuit 74 to the control signal terminals a in each of the stages in the shift register 50. Similarly, the shift line 72 is connected through a delay circuit 76 to the control signal terminals b in each of the stages in.the shift register 50 also. The delay circuits 74 and 76 exhibit substantially identical delays. Shift, or control signal, pulses P and P are applied to the shift lines 70 and 72 to transfer binary information stored in the shift register 50 into the shift register 60. For purposes of the present discussion, a positive-going voltage of given value is assumed to represent a 1 and ground to represent a 0. The control signal pulse's'P .and P may, for example, be generated by a pair of oneshot multivibrators (not shown). The pulse P increases from a quiescent value representing a 0 to a positive value representing a 1 and then drops back to the value representing 0. The pulse P on the other hand, decreases from a quiescent level representing a 1 to a level representing a 0 and then rises again to the level representing 1. Thus, it is apparent that in the absence of the pulses P and P the control terminals a and b of the registers 50 and 60 have applied thereto signals of opposite binary value. This is the memory or A type (see FIGURE 2) of operation and the binary signals stored in the registers 50 and 60 remain as they are regardless of other changes.

To shift information from the register 50 into the register 60, the control pulses P and P are generated one after another, in either order. Assume that pulse P occurs first. When the leading edge of pulse P is generated, the control terminals a and b in all the stages of register 60 receive a 1. This is the B type of operation (see FIGURE 2) and if a 1 is present in a stage of register 50 it is transferred into the corresponding stage-of the register 60.

At the termination of the pulse P the shift line 70 drops back to the binary level. The leading edge of the pulse P then drops the shift line 72 to the binary 0 level so that a and b of all stages are 0. This is the C type of operation (see FIGURE 2). Any 0 present in a stage of register 50 is transferred into the corresponding stage register 60.

At the expiration of the pulse P the control signal b returns to the binary 1 level. The control signals a and b are then of opposite binary values and the register 60 is operating in the manner shown at A in FIGURE 2.

The delay circuits 74 and 76 are provided to delay the pulses P and P so that binary signals are shifted into the register 50 subsequent to the shifting of binary signals into the register 60. As the pulses progress in one direction from right to left, binary information is effectively shifted in the opposite direction, from left to right.

The input signal x to the register 50 may be derived from another four bit register of the same form, from the common bus in a computer, or even from the other register 60. In the latter case the output of gate 60a could be fed to the input of gate 50b, gate 60b to gate 50c, and so on, so that registers 50 and 60 together act as a bit-serial shift register. The shifting of information into the register 60 from either the register 50 or a bus line is essentially a two-step operation. In the first step, 1 signals are transferred and in the second step, 0 signals are transferred. The transfer may be effected in the reverse order by generating the P pulse before the P pulse. No inter-stage coupling or gating is needed to transfer signals into the register 60.

A portion of a second system employing the building blocks of the invention is shown in FIGURE 14. The system includes cascaded gates 120 and 122, inverters 124, 126 and 128, various interconnections among the gates and feedback connections. (The inverters, while shown separately need not be separate circuits. The logical inversion may instead be performed within the gate. For example, 6 may be obtained from the output terminal of a threshold gate such' as described in Clapper Patent No. 3,038,091, dated June 5, 1962, and 0 from the other output terminal of the same gate.) The gates of FIGURE 14 are analogous to the gates of FIGURE 5, r

however, one of the feedback connections in FIGURE 14 corresponds to a control signal connection in FIG- URE 5 but with weight 2 and one of the inputs in FIG- URE 14 corresponding to a third control signal input in FIGURE 5 is permanently connected to a permanent bias level of 0. As an alternative, threshold gates with four inputs of weights 1, 1, 2, 2 and with a threshold T=4 may be employed, and the 0 bias input omitted. (This gate is the equivalent of the gate shown.)

The arrangement of FIGURE 14 may be employed in the control logic circuits of any asynchronous computer, for example, in the control logic circuits either for a multiplier, or in an arrangement for implementing an instiuction-fetch command. Each threshold gate corresponds to one possible state of the control unit, and normally (except for short transition times) only one gate in the chain at a time has an output signal of 1. The transition from one state to the next may take place at some predetermined time (in a synchronous situation) or upon completion of some particular task (in an asynchronous situation).

In one type of circuit operation, the control signal 0 is sent to a processing portion of the computer and initiates theer some process. The signal x is the return signal from the processor or from a time-pulse generator and it indicates that the process has been completed. This signal causes gate to become set (four of the input weights have the value of 1), so that control signal c is sent to the processor, and at the same time signal 0 is inhibited. The latter occurs because 5 the signal sent to the preceding stage (not shown), has changed to 0 and x (not shown) is also 0. The circuit state then remains stable until the return signal x initiates the transition of the circuit to its next state, that is, gate 122 becomes set, gate 120 becomes reset, signal 0 is sent to the processor, and signal is inhibited. Other stages (not shown) after 122 operate in the same way.

In more detail, note that in the circuit illustrated when c =c =c =O, the situation is stable-the control is in some state not represented in the figure. This is because the total number of input weights corresponding to 1 is at most three (a possible x, and the inverted signal 5 from a later stage) and the threshold of 4 is not attained, so the outputs 0 remain 0.

Suppose now that c, becomes a 1 indicating that the machine is in a state represented by a gate not shown, 'but that gate 120 may be the next state desired. No change takes place, however, as long as the return signal x is 0, and the control system waits. When x =1, then a total of four input weights are 1x c and 5 so the output c becomes 1, and this signal causes the next process to be performed by the machine to start. Also, 0 is fed back through an inverter to set 0 :0 in a manner to 'be illustrated below for c However, even when 0 becomes 0, 0 remains 1 because of the feedback of 0 :1.

The control system now waits again until x becomes 1. When it does, gate 122 has a total input weight of four ls and so c becomes 1. The signal 0 :1 causes the next process to start. At the same time, 5 becomes 0, so the total input weight at gate 120 is at most three ls (x possibly, and 0 so 0 becomes 0.

The operation described above continues for any num- 'ber of cascaded stages. A stage will be turned on if the preceding stage is on and if the immediately following stage is off. Each time a stage goes on, it automatically turns off the preceding stage.

In the example above, a transition of the circuit to the next state is accomplished by a simple return or time pulse signal but, in general, other circuits may 'be used, where more complicated logic is performed. For example, it may be required that the transition to the next state take place when two return signals are simultaneously present. In this case, circuits similar to the one of FIG- URE 10 may be used (except with more control lines), for the cascaded stages of FIGURE 14.

The circuit of FIGURE 14 may be employed in a configuration which includes multiple parallel branches by using a return signal x for acuating one branch and a complementary return signal x, for another branch.

In the embodiment of the invention illustrated, the complementary feedback signal 5, generated by stage i, is applied to the immediately preceding stage (i1). However, in general, it is applied to the (i "th) stage where j may be 1 or some other integer.

It is also to be appreciated that while in the embodiment of FIGURE 14 there is only a signal information signal (the return signal 1:) in general there may be up to p such signals, where p is an integer such as 1, 2, 3 and so on. In the case in which p is 1 the logic function performed by the circuit is the identity function, that is, c =x In the case in which p is greater than 1, the circuit may perform some logic function other than this. For example, if p=3 and the returns to the ith stage are x x x the output of the ith stage when (c,-=l) may be equal to MAI (x x x or x x x or x +x +x and so on. The logic functions it is desired to perform determine the particular one(s) of the gates which have been discussed to be employed as the stages of the network.

p information signals to each gate is less than T, and the sum of the weights of the complementary input signal and the signal from the preceding stage applied to each gate is less than T. v

There are a number of important advantages of using threshold gates to generate'control signals in the manner discussed above. The design is very simple-each gate corresponds to a state in the designers state diagram. Malfunctions are very easily discovered since gates are used for only one purpose, ,not shared .between many dilferent states. And, the =numberff gates required is small, since logical functionsdetermination of when state-transitions should take place are combined with the memory functionremembering which state. the machine is inboth in a single gate.

A multiplier which-employs the buildingblocks of .the invention is shown in FIGURE 16. To simplify the drawing, the control signal terminals and the feedback terminals of the various building blocks are not shown. The meaning of the symbols employed in FIGURE 16 is given in FIGURE 15. Note that the flip-flop is the circuitof FIGURE 1; the AND flip-flop is the circuit of FIGURE 5 since one ofthe xs, in practice, is a constantthroughout a complete multiplication cycle and therefore is considered as acontrol signal; the carry'flip-flop is the cirpuit of FIGURE 10; the majority flip-flop is essentially r the circuit of FIGURE 11; and the double flip-flop is the circuit of FIGURE 12.

-The inputs-c and 0, refer to the clock ortimin-g pulses. In practice, there are four such pulses c c c -and c Initially, c =0, 1, c =0and c =-1. A notation of. two

- a; number of cases, an input passes through a small a circlebeforearriying.at.;a block. The circle indicates logical inversion. For example, in the case of themajority flip-flop block. (MAJ) of FIGURE l5'when x is 0, a v1 --is applied-to the majority flip-flop block. The logical inversion may be accomplished by a separate inverter,

however, in .practice the inversionoccurs within a block. One ,Way in which this may be done is to employ the complementary output of the stage generating the signal inthe manner already discussed. I

While not shown it is to be understood that all of the 1 blocks in the multiplier, of FIGURE 16 are initially ina -state such-that they produce 0 outputs. This state may be achieved in one of a number of ways. As one example, the multiplier maybe made to multiply000 000j As another example, one. actually employed in a practical circuit.

there may be an overriding reset connection to each buildingflblock (not shown) which appliesan input to that building block sufficient to force the output to 0. Ida 'transistorized threshold gate building block, this may be accomplished, for example, by applying through a diode a signal of appropriate polarity and level directly to the base electrode of a transistor in the block.

The multiplicationalgorithrn carried out by the multiplier of FIGURE 16 is given below. The specific example chosen is the multiplication of 5 (101) by 7 (111) to obtain a product of 35 (1000 11).

Multiplicand. Multiplier.

Initial sum.

Initial carry.

(a) Firstpartial product.

Sum.

Carry.

Second partial product (shifted one place to left).

Final product (normal addition h and i) Note that in each step of the multiplication, the sum, tarry, and partial product are added and any carries which result from this addition are separately stored. Only in the final step is an addition carried out in the normal way, that is, wherethe carry ripples from bit to bit. Because of the absence of carry ripple except for the final step, and because the storage of partial products, sums and carries occurs in the multiplier itself, the multiplication time is extremely fast. In a practical multipler the multiplication time may be 40 nanoseconds or less per multiplier bit. For three bits, the total" time is 12O'nanoseconds plus the relatively short ripple time through the gates 260, 280, 270, 286. n In the operation of the multiplier of FIGURE 16, the three multiplier bits are applied to leads 152, 154 and 156, respectively, and the three multiplicand bits are applied to leads 158, and 162, respectively. The significance of the 'bits' is indicated by the numbers 2, 2 2 respectively. The first half cycle of multiplication cycle starts at time periods 3 and 4. During time period 3, c is changed from O to 1 to 0 and during the time period 4, c is changed from 1 to 0 to 1. During the first occuring time period of c and 0 (that is, the length of time'from the start of 0 to the end of 0 the first half cycle) U is changed from 1 to 0 and upon the termination of the half cycle U changes back to 1. During the remainder of the multiplication, U =1 and U =0. (It may be observed from FIGURE 15 that U -and U are control inputs to the double flip-flops.) 7 Assume that the multiplier is 111 and themultiplicand is 101, as in the example above. During the time period foccupie'dby c ofthe firsthalf cycle, 0;, is 0, 0 is O, U -is 0 and .U is '0 sothat six of the thirteen input weights to double flip-flops 164, 168 and 170' are 1 Since the multiplier is 1, 1,; 1, the x inputs to each double flip-flop is 164, 16 8 and 170 is 1, and each such ;flip-flops threshold of 7 is attained. These flip-flops thereupon produce ones at output leads 172, 174 and 176 and the flip-flop 164 feeds back its 1 output to AND gates 178, 1-80'and 182. a

During thev second half cycle, c changes from 0 to 1 to 0 and then changes from 1 to (Ho 1.During the intervalof 0 AND gates 182 and 178 become .set since, in each case, c =c =x =x =1.-(see FIGURE 15) -so that four of the seven input weights are 1; During the "second time period, c and c both equal 0, however, the feedback connection of-AND gates 182 and 178 and-the multiplicand signal inputs (which remain constant throughout the multiplication, and can be'considered as as control signals),"to these ANDgates maintain these gates in the 1' state. After the second'tit'ne period c c and AND gates 178, 180and 1,82 continue to store the information transferred to these 'igates, namely 1, 0 and 1, respectively.

During the'same p'eriodas discussed above, namely, the period during which AND gates 178, 180 and 182 are operated, the same clock pulses c and 0 areapplied to flip-flops 184 and 186 and majority gate 188. Flipflops 184 and 186 receive 1s on leads 172 and 174, re-

15 spectively and store these 1s. Majority gate 188 receives a 1 on lead 176 and a on lead 190 and a 0 on lead 192. However, this last 0 is inverted at gate 188 so that two of three inputs are 1 and majority gate 188 therefore stores a 1.

During the next two time intervals, the gates in the second cascade 200 are operated. Flip-flop 202 receives and stores a 1. Carry flip-flop 204 receives a O on lead 206 and a O on lead 208 and therefore stores a 0. Majority gate 210 receives a 0 on lead 212 and a 0 on lead 214 and therefore stores a O. Flip-flop 216 receives a 0 on lead 218 and therefore stores a 0. Carry flip-flop 220 receives a 0 on lead 222 and a 1 on lead 224 and since its output at 192 is a 0, it continues to store a 0. Majority gate 226 receives a 0 at lead 228 and a 1 at lead 230 and a O at lead 232, however, the 0 lead 232 is inverted at the gate so that majority gate 226 becomes set and stores a 1. Double flip-flop 170 receives a 1 at lead 156 and a 0 at lead 157. Since U =1, this double flip-flop stores a 0 (see FIGURE 15.) Double flip-flop 168 receives a 1 at lead 154 and a 1 at lead 233 and therefore stores a 1. Double flip-flop 164 receives a 1 at lead 152 and a 1 at lead 235 and therefore stores a 1.

The operation discussed above and the succeeding cycles of, the circuit operation is given in the table below. The 1s and Os within the table indicate the outputs of the gates.

Half cycle 0 0 0 0 0 0 1 1 1 First U =0, 11:0 1 0 0 0 0 1 0 1 1 Third U =1, U =0 1 0 1 0 0 1 0 1 1 Fifth U2=1, U =0 1 0 1 0 1 1 0 1 1 Seventh Uz=1, U =0 Gate number Half cycle 1 0 1 0 0 0 0 1 1 1 Second 1 0 1 1 0 0 0 1 1 1 Fourth 1 0 1 1 0 1 0 1 1 1 Sixth 1 0 1 1 0 1 1 0 1 1 Eighth The four threshold gates 260, 280, 270 and 286 shown at the lower left of FIGURE 16 perform the final addition involving carry ripple with one stage of carry lookahead. Gate 260 receives a 1 at lead 262, a 0 at lead 264, a 1 at lead 266 and a l at lead 268. Accordingly, the threshold 4 of the gate is equaled and it produces a 1 output. This is the 2 bit.

Threshold gate 280 receives a 1 lead at lead 281 and a 1 at lead 284 and accordingly, produces a 1 output. Threshold gate 270 receives a 0 at lead 274 and a 1 at lead 275. This gate also receives the inverted output of gate 260. Accordingly, only two of the five inputs are 1 and the gate produces a 0 output. The 2 bit therefore is 0.

Threshold gate 286 receives a continuous value of 0 and receives a 1 from gate 280. This 1 is inverted so that three of the' five inputs to gate 286 are 0. Accordingly, gate 286 produces a 0 output, that is, the 2 bit equals 0. It may be observed, from the table, that the 2 2 and 2 bits are 0, 1, 1, respectively. Accordingly, the final product is l000l1=35 which is the correct answer.

One final point which is implicit in the discussion of the operation of the multiplier is the use of groups of stages such as 220, 226, 170, 248 and 188 and 204, 210,

16 What is claimed is: 1. A circuit for performing both storage and logic functions comprising, in combination:

a threshold gate having an input circuit and an output circuit; means for applying n input signals x x with respective weights W1 w to said input circuit to said gate, where n is an integer equal to at least 1 and W1 w are integers; feedback means for feeding back the signal present at the output circuit of the threshold gate to the input circuit to the gate with weight w, where w is an integer at least equal to 2 and greater than the sum of W1 '|-w and means for elfectively applying m control signals 0 c to the input circuit to said gate with respective weights v v where m is an integer greater than 1 and v v are integers equal to at least l. -2. The circuit of claim 1, wherein n=1, w ==1, w=2, m=2 and v =v 1, and wherein said gate has a threshold vof3.

216, 244 and 246, as adders with built in storage. The

3. The circuit of claim 1, wherein n=1, W 1, w=2, m=4 and v =v =v =v =l, and wherein said gate has a threshold of 4.

4. The circuit set forth in claim -1, wherein n=2, w =w =1, w=3, m=2, v =v ==1, and wherein sai gate has a threshold of 4.

5. The circuit set forth in claim 1, wherein n=3', w =w =w =l, w:4, m=3, v- =2. v =v =1, and wherein said gate has a threshold of 6.

6. The circuit set forth in claim 1, wherein n==2, w =2, w =1, w=4, m=4, v =v =2, v =v =1, and wherein said gate has a threshold of 7.

7. The circuit set forth in claim 1, wherein 'n=3, w =w =w =1, w=4, m=2, v =v =1, and wherein said gate has a threshold of 4.

8. In combination: I

a threshold gate having an input circuit, an output circuit and a threshold of at least 3;

means for applying n information signals x .x, to said gate with respective weights W1 w' where n is equal to at least 1 and W1 w are integers equal to at least 1;

means coupled between the output and input circuits of said gate for feeding back to the input circuits of said gate a signal y with weight w, where w is an integer equal to at least 2; and

means for controlling the gate to operate as one of a storage circuit which is insensitive to the values of the n information signals and a circuit which realizes at least one logic function of y and at least one of x x I 9. The circuit of claim 8, wherein said mast-named means comprises means for controlling the gate to operate as one of a storage circuit which is insensitive to the values of the n information signals and a circuit which realizes an AND function of y at least one of x x 10. The circuit of claim 8, wherein said last-named means comprises means for controlling the gate to operate as one of a storage circuit which is insensitive to the value of the n information signals and a circuit which realizes a majority function of y and at least two of x x A 11. The circuit of claim 9, wherein said last-named means comprises means for controlling the gate to operate as one of a storage circuit which is insensitive to the values of the m information signals, a circuit which realizes an AND function of y and at least one of x x and a circuit which realizes an OR function of y and at least one of x x 12. The combination set forth in claim 8, wherein 11:2, w =w =l, and wherein the last-named means includes means for controlling the gate to realize the logic functions y( 1+ 2), y+ r 2 and U. 1. 2)-

13. The combination set forth in claim 8, wherein n=3, w =w =w =1, and wherein the last-named means comprises means for controlling the gate to realize the logic functions y-MAJ(x x x and y+MAJ(x x x 14. The combination set forth in claim 13, wherein the last-named means comprises means for controlling the gate to realize the logic function MAI(x x x 15. The combination of claim 8, wherein n=2, w =2, w =1, and wherein the hast-named means comprises means for controlling the gate to realize the functions y-l-x and yx 16. The circuit of claim 8, wherein said last-named means comprises means for controlling the gate to realize an OR function of y and at least one of x x 17. In combination:

a threshold gate having an input circuit and an output circuit; means for applying 11 input signals x x with respective weights W1 w to said input circuit to said gate, where n and W w are integers;

feedback means for feeding back the output signal of the threshold gate to the input circuit to the gate with weight w, where w is an integer greater than the sum of w +w means for causing said gate to store information comprising means for applying m control signals c to the input circuit to said gate with respective weights v v where m is an integer greater than 1, v v are integers, the weight of the control signals representing 0 is equal to the weight of the control signals representing 1, and the weight of the feedback signal plus one half the total weight of the control signals at least equal the threshold of the gate; and

means for causing the gate to perform logic functions other than the memory function comprising means for changing the values of the control signals.

18. A control circuit comprising, in combination;

a plurality of cascade connected threshold gates, each having an input circuit and an output circuit;

means for applying a signal from the output circuit of each gate as the first input signal to the input circuit of the following gate;

means for applying a feedback signal from the output circuit of each gate to the input circuit of the same gate;

means for applying the complement of the feedback signal to each gate to the input circuit of a preceding gate;

means for applying P information signals to each gate,

where P is an integer; and

each gate having a threshold T, where the sum of the weights of the complementary input signal, the first input signal and at least one of the information signals to each gate is at least equal to T, the sum of the weights of the complementary input signal and the feedback signal to each gate is at least equal to T, the sum of the weights of the feedback signal and the P information signals to each gate is less than T, and the sum of the weights of the complementary input signal and the first input signal to each gate is less than T.

References Cited FOREIGN PATENTS 6/1961 Australia.

OTHER REFERENCES ROY LAKE, Primary Examiner JAMES B. MULLINS, Assistant Examiner US. Cl. X.R. 3072l1, 238, 290 

